PLC program sequential logic design method

(1) overview
 
Sequential logic design method is suitable for the output signals of the status change of the PLC has some chronological situation, when in programming according to draw sequence diagram of the output signal, streamlining the state transitions and transition conditions, examine the output and input and internal contacts and the relationship, and make the appropriate reduction. In General, the sequential logic design method should be used with the experience, or will probably make the logical relationship is too complex.
 
(2) sequential logic design method of programming steps
 
1) according to the requirements, specific number of input/output signals.
 
2) clear the timing relationship between the input and output signals, draw sequence diagrams from the various input and output signals.
 
3) sequence diagram can be divided into several sections, find the demarcation point between the sectors, identify boundary point output signal conversion and conversion conditions.
 
4) PLC I/O, internal auxiliary relays and timers/counters for distribution.
 
5) lists the output signals of a logical expression, draw a ladder diagram according to logical expressions.
 
6) debugging through simulation, verify that the program is in line with requirements, combined with the experience design was used to further modify the program.
 
(3) examples of sequential logic design
 
1) control requirements. There are A1 and A2, two electric motors, after pressing the Start button, run A1 10min, stop 5min,A2 contrary to A1, A2 when A1 stops running, A1 A2 stops at run time, so the cycle, until the stop button is pressed.
 
2) I/O allocation. X0 as the Start button, X1 for the stop button, Y0 to A1 motor contactor coil Y1 for the A2 motor contactor coil.
 
3) draw sequence diagrams. In order to make the logical relationship clear, running with M0, as an auxiliary relay control relays, and T0 run time control A1, T1 control A1 parking time. Draw sequence diagrams on request, as shown in Figure 5-35. As can be seen from the diagram, blinking T0 and T1 circuits, logic expressions

Ladder Diagram

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